IEEE CEDA / Taiwan MOE, ICCAD 2015 Contest

Incremental Timing-driven Placement

Myung-Chul Kim and Jin Hu, IBM Corporation, TX/NY, USA

0. Announcements

1. Important Dates

2. Evaluation Results

3. Contest Description (contest_description.pdf)

a) Introduction

    Incremental timing-driven placement is one of the crucial steps in the RTL-to-GDSII VLSI design flow. This step optimizes locations of circuit elements to reduce the interconnect delay for timing critical paths, which is becoming a major limiting factor for timing closure in deep-submicron VLSI designs.

    Although there have been significant advances in the quality of placement algorithms by way of the ISPD-2005, ISPD-2006, ISPD-2011, ICCAD-2012, and ICCAD-2013 placement contests, the most research activities have been driven by innovations in early placement in the flow whereas incremental timing-driven placement is often considered as an after-thought in the flow and implemented as a mixture of ad hoc techniques. The state-of-the-art incremental timing-driven placement algorithms are often hard to be compared, and individual impact of the technique in the flow remains unclear.

    Nevertheless, the need for high performance incremental timing-driven placement continues to grow in modern design closure flows. Due to the lack of accurate interconnect information during early placement, placement engines typically try to optimize total wirelength, which is unaware of interconnect length distributions for individual timing paths. During the optimization of routability, density profiles, or other objective, their timing impacts are often harmed and can generate timing violations / other timing-critical paths. Thus, it is important to recover timing while maintaining the solutions that the optimizations provided. Some important metrics that need to be carefully monitored to preserve the overall quality of a given placement include: (a) placement density, (b) pin density, and/or (c) routing congestion. While optimizing wirelength, the impact on such metrics should remain well-bounded. Meanwhile, at different points in the flow, one needs different degrees of timing-driven placement -- earlier one can allow larger moves in order to improve timing. Late in the flow, only small local moves that clearly improve the design can be accepted. This contest will frame the problem and in such a way as to capture incremental timing-driven placement that spans the gamut of possible needs in a design closure flow. Some examples include: (a) the relative trade-offs between optimizing timing and preserving the overall quality of an input placement, or (b) placement techniques required to obtain good timing and routing profile, in case the tool needs to explicitly limit the maximum movement from a given placement.

b) Contest Objectives

For a given legal circuit placement of a netlist, timing-driven placement incrementally seeks legal locations of the circuit elements to optimize timing of the network subject to the given constraints. The goal of the ICCAD 2015 contest is to evaluate the performance and impact of different incremental timing-driven placement algorithms after initial wirelength / routability-driven placement during physical synthesis. Specific objectives of the proposed contest include:

c) Evaluation Methodology

The quality of the placement solutions will be evaluated on the following metrics:

The optimization should be subject to the following constraints:

For each benchmark design, the teams will be ranked using the contest evaluation metric. The evaluation metric will both consider the quality of placement solutions and runtimes. The team with the lowest total rank across all the contest designs would win the contest. See details here: contest_description.pdf.

4. Download

a) Timer

For this contest, we are using UI-Timer 2.0, based on the 1st place timer from the TAU 2014 and the 2nd place timer from the TAU 2015 Timing Contests. There are two versions available: one as a binary, and one as APIs to use for embedding into your placement tools. For more information about timer input and usage (e.g., incremental timer usage by feeding a modified spef), please visit the TAU 2015 Contest website, and look at Resources -> TAU 2015 contest_file_formats.

b) Parser/Evaluation Script

The start's kit includes benchmark parser (not generic, only for use in the contest), Steiner tree generator, spef writer, usage of timer APIs, evaluation procedures, and technology/timer-related files that all you need to evaluate timing on testcases. A `simple' testcase is also included. Feel free to use/modify the evaluation script source codes (*.cpp, *.h, makefile) to build your own infrastructure.

c) Benchmarks

Disclaimer: The benchmarks are reversed-engineered from bookshelf-format files by individual academic researchers using their published methods/logic mapping. Therefore, the logic and timing information of the benchmarks can be different from that of the actual designs. Also, please note that maximum cell displacement limits, target utilization and clock periods may be subject to changes during the final evaluation.

5. Submission Information

a) Contest Machine Configuration:

b) Submission Guidelines:

6. FAQ